Synopsys is looking for engineering graduates/PG students to work as interns in the field of VLSI.
Job duties and responsibilities:
The role will be focused on VLSI design in the following areas related to connectivity protocols: DDR PHY.
The nature of the role will be:
- VLSI Design of sub-blocks/exploration of latest features and standards.
- Based on project assigned, the job would involve one or more of the following activities: Verilog/System Verilog
- Exposure to UVM methodology, working with EDA tools like Design Compiler for Synthesis, SpyGlass for Lint, VCS for simulation.
Qualifications and Experience required:
- Must have completed Bachelors’ degree in Electronics/ Electrical Engineering.
- Partial completion of MS/MTech preferable. (Electrical/Electronics/VLSI/MicroElectronics or allied specializations.)
- Minimum 7.0 CGPA/ 70% in Bachelor’s in Engineering and 7.5 CGPA in Master’s till the current semester.
- Need to be backed with consistently high academics in 10th std and 12th standard.
- Strong fundamentals in Digital electronics.
- HDL Languages coding experience preferably in Verilog/System Verilog.
Location: Bangalore, KA